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low power, high slew rate, wide bandwidth, jfet input operational amplifiers quality bipolar fabrication with innovative design concepts are employed for the mc33181/2/4, mc34181/2/4 series of monolithic operational amplifiers. this jfet input series of operational amplifiers operates at 210 m a per amplifier and offers 4.0 mhz of gain bandwidth product and 10 v/ m s slew rate. precision matching and an innovative trim technique of the single and dual versions provide low input offset voltages. with a jfet input stage, this series exhibits high input resistance, low input offset voltage and high gain. the all npn output stage, characterized by no deadband crossover distortion and large output voltage swing, provides high capacitance drive capability, excellent phase and gain margins, low open loop high frequency output impedance and symmetrical source/sink ac frequency response. the mc33181/2/4, mc34181/2/4 series of devices are specified over the commercial or industrial/vehicular temperature ranges. the complete series of single, dual and quad operational amplifiers are available in the plastic dip as well as the soic surface mount packages. ? low supply current: 210 m a (per amplifier) ? wide supply operating range: 1.5 v to 18 v ? wide bandwidth: 4.0 mhz ? high slew rate: 10 v/ m s ? low input offset voltage: 2.0 mv ? large output voltage swing: 14 v to +14 v (with 15 v supplies) ? large capacitance drive capability: 0 pf to 500 pf ? low total harmonic distortion: 0.04% ? excellent phase margin: 67 ? excellent gain margin: 6.7 db ? output short circuit protection ? offered in new tssop package including the standard soic and dip packages ordering information op amp function device operating temperature range package single mc34181p mc34181d t a = 0 to +70 c plastic dip so8 mc33181p mc33181d t a = 40 to +85 c plastic dip so8 dual mc34182p mc34182d t a = 0 to +70 c plastic dip so8 mc33182p mc33182d t a = 40 to +85 c plastic dip so8 quad mc34184p mc34184d mc34184dtb t a = 0 to +70 c plastic dip so14 tssop14 mc33184p mc33184d mc33184dtb t a = 40 to +85 c plastic dip so14 tssop14 on semiconductor ? semiconductor components industries, llc, 2002 march, 2002 rev. 2 1 publication order number: mc34181/d mc34181,2,4 mc33181,2,4 d suffix plastic package case 751 (so8) p suffix plastic package case 626 p suffix plastic package case 646 d suffix plastic package case 751a (so14) pin connections (single, top view) (dual, top view) (quad, top view) 4 23 1 pin connections offset null v ee v ee inputs 1 output 1 inputs nc v cc output offset null inputs 2 output 2 v cc 1 2 3 4 8 7 6 5 + 1 2 3 4 8 7 6 5 1 2 1 2 3 4 5 6 78 9 10 11 12 13 14 inputs 1 output 1 v cc inputs 2 output 2 output 4 inputs 4 v ee inputs 3 output 3 - + - + - + -- - + + - + - 1 8 1 8 14 1 14 1 dtb suffix plastic package case 948g (tssop14) 14 1
mc34181,2,4 mc33181,2,4 http://onsemi.com 2 maximum ratings rating symbol value unit supply voltage (from v cc to v ee ) v s +36 v input differential voltage range v idr note 1 v input voltage range v ir note 1 v output short circuit duration (note 2) t sc indefinite sec operating junction temperature t j +150 c storage temperature range t stg 60 to +150 c notes: 1. either or both input voltages should not exceed the magnitude of v cc or v ee . 2. power dissipation must be considered to ensure maximum junction temperature (t j ) is not exceeded (see figure 1). q 8 internal bias network neg pos v cc v o v ee j 1 j 2 q 9 q 7 d 3 d 1 c 1 r 6 d 2 r 7 c 2 q 4 q 6 q 5 i 4 r 5 r 4 r 2 q 3 i 3 r 3 r 1 q 2 q 1 null offsets mc3x181 (single) only 1 5 1 5 v ee mc3x181 input offset voltage null circuit 25 k w - + + representative schematic diagram (each amplifier)
mc34181,2,4 mc33181,2,4 http://onsemi.com 3 dc electrical characteristics (v cc = +15 v, v ee = 15 v, t a = 25 c, unless otherwise noted.) characteristics symbol min typ max unit input offset voltage (r s = 50 w , v o = 0 v) single t a = +25 c t a = 0 to +70 c (mc34181) t a = 40 to +85 c (mc33181) dual t a = +25 c t a = 0 to +70 c (mc34182) t a = 40 to +85 c (mc33182) quad t a = +25 c t a = 0 to +70 c (mc34184) t a = 40 to +85 c (mc33184) v io e e e e e e e e e 0.5 e e 1.0 e e 4.0 e e 2.0 3.0 3.5 3.0 4.0 4.5 10 11 11.5 mv average temperature coefficient of v io (r s = 50 w , v o = 0v) d v io / d t e 10 e m v/ c input offset current (v cm = 0 v, v o = 0v) t a = +25 c t a = 0 to +70 c t a = 40 to +85 c i io e e e 0.001 e e 0.05 1.0 2.0 na input bias current (v cm = 0 v, v o = 0v) t a = +25 c t a = 0 to +70 c t a = 40 to +85 c i ib e e e 0.003 e e 0.1 2.0 4.0 na input common mode voltage range v icr (v ee +4.0 v) to (v cc 2.0 v) v large signal voltage gain (r l = 10 k w , v o = 10 v) t a = +25 c t a = t low to t high a vol 25 15 60 e e e v/mv output voltage swing (v id = 1.0 v, r l = 10 k w ) t a = +25 c v o + v o +13.5 e +14 14 e 13.5 v common mode rejection (r s = 50 w , v cm = v icr , v o = 0 v) cmr 70 86 e db power supply rejection (r s = 50 w , v cm = 0 v, v o = 0 v) psr 70 84 e db output short circuit current (v id = 1.0 v, output to ground) source sink i sc 3.0 8.0 8.0 11 e e ma power supply current (no load, v o = 0 v) single t a = +25 c t a = t low to t high dual t a = +25 c t a = t low to t high quad t a = +25 c t a = t low to t high i d e e e e e e 210 e 420 e 840 e 250 250 500 500 1000 1000 m a
mc34181,2,4 mc33181,2,4 http://onsemi.com 4 ac electrical characteristics (v cc = +15 v, v ee = 15 v, t a = 25 c, unless otherwise noted.) characteristics symbol min typ max unit slew rate (v in = 10 v to +10 v, r l = 10 k w , c l = 100 pf) a v = +1.0 a v = 1.0 sr 7.0 e 10 10 e e v/ m s settling time (a v = 1.0, r l = 10 k w , v o = 0 v to +10 v step) to within 0.10% to within 0.01% t s e e 1.1 1.5 e e m s gain bandwidth product (f = 100 khz) gbw 3.0 4.0 e mhz power bandwidth (a v = +1.0, r l = 10 k w , v o = 20 v pp , thd = 5.0%) bw p e 120 e khz phase margin (10 v < v o < +10 v) r l = 10 k w r l = 10 k w , c l = 100 pf f m e e 67 34 e e degrees gain margin (10 v < v o < +10 v) r l = 10 k w r l = 10 k w , c l = 100 pf a m e e 6.7 3.4 e e db equivalent input noise voltage r s = 100 w , f = 1.0 khz e n e 38 e nv/ hz equivalent input noise current f = 1.0 khz i n e 0.01 e pa/ hz differential input capacitance c i e 3.0 e pf differential input resistance r i e 10 12 e w total harmonic distortion a v = 10, r l = 10 k w , 2.0 v pp < v o < 20 v pp , f = 1.0 khz thd e 0.04 e % channel separation (r l = 10 k w , 10 v < v o < +10 v, 0 hz < f < 10 khz) e e 120 e db open loop output impedance (f = 1.0 mhz) |z o | e 200 e w 8/14 pin plastic so-8 so-14 figure 1. maximum power dissipation versus temperature for package variations figure 2. input common mode voltage range versus temperature t a , ambient temperature ( c) d p, maximum power dissipation (mw) -55 -40 -20 0 20 40 60 80 100 120 140 160 t a , ambient temperature ( c) icr v , input common mode voltage range (v) -55 -25 0 25 50 75 100 125 v cc = +3.0 v to +15 v v ee = -3.0 v to -15 v d v io = 5.0 mv v cc (v cm to v cc ) v ee 2400 2000 1600 1200 800 400 0 0 -1.0 -2.0 3.0 2.0 1.0 0 tssop-14
mc34181,2,4 mc33181,2,4 http://onsemi.com 5 v ee v cc v cc = +15 v v ee = -15 v t a = +25 c figure 3. input bias current versus temperature figure 4. input bias current versus input common mode voltage figure 5. output voltage swing versus supply voltage figure 6. output saturation voltage versus load current figure 7. output saturation voltage versus load resistance to ground figure 8. output saturation voltage versus load resistance to v cc t a , ambient temperature ( c) ib i, input bias current (na) -55 -25 0 25 50 75 100 125 v cc = +15 v v ee = -15 v v cm = 0 v v icr , input common mode voltage (v) -10 -5.0 0 5.0 10 v cc = +15 v v ee = -15 v t a = 25 c v cc , |v ee |, supply voltage (v) 0 2.0 4.0 6.0 8.0 10 12 14 16 v o , output voltage swing (v) r l connected to ground t a = 25 c r l = 10 k i l , load current (ma) sink 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 v cc = +15 v v ee = -15 v t a = +25 c source sat v , output saturation voltage (v) r l , load resistance to ground ( w ) 1.0 k 10 k 100 k 1.0 m v ee v cc v cc = +15 v v ee = -15 v t a = +25 c r l , load resistance ( w ) 1.0 k 10 k 100 k 1.0 m v cc v ee sat v , output saturation voltage (v) sat v , output saturation voltage (v) ib i, input bias current (na) 1000 100 10 1.0 0.1 0.01 0.001 20 15 10 5 0 40 30 20 10 0 0 -1.0 -2.0 -3.0 +3.0 +2.0 +1.0 0 0 -1.0 -2.0 -3.0 3.0 2.0 1.0 0 0 -1.0 -2.0 -3.0 3.0 2.0 1.0 0
mc34181,2,4 mc33181,2,4 http://onsemi.com 6 100 10 1.0 a v = 1000 v cc = +15 v v ee = -15 v v o = 2.0 v pp r l = 10 k w t a = 25 c v cc = +15 v v ee = -15 v r l = 10 k w thd = 1.0% t a = 25 c 100 10 a v = 1000 1.0 v cc = +15 v v ee = -15 v v cm = 0 v v o = 0 v d i o = 10 m a t a = 25 c a , open loop voltage gain (db) figure 9. output short circuit current versus temperature figure 10. output impedance versus frequency figure 11. output voltage swing versus frequency figure 12. output distortion versus frequency figure 13. open loop voltage gain versus temperature figure 14. open loop voltage gain and phase versus frequency t a , ambient temperature ( c) sc i, output short circuit current (ma) -55 -25 0 25 50 75 100 125 sink source v cc = +15 v v ee = -15 v r l 0.1 w v id = 1.0 v f, frequency (hz) o |z|, output impedance () w 100 1.0 k 10 k 100 k 1.0 m f, frequency (hz) 1.0 k 10 k 109 k 1.0 m , v o output voltage swing (v p-p ) f, frequency (hz) thd, total harmonic distortion (%) 10 100 1.0 k 10 k 100 k vol a, open loop voltage gain (v/mv) t a , ambient temperature ( c) -55 -25 0 25 50 75 100 125 f, frequency (hz) vol 1.0 10 100 1.0 k 10 k 1.0 m 10 m 100 m 100 k phase gain , excess phase ( degrees ) f 30 20 10 0 300 200 100 0 30 24 18 12 6 0 1.0 0.8 0.6 0.4 0.2 0 70 60 50 40 30 20 100 80 60 40 20 0 v cc = +15 v v ee = -15 v r l = 10 k w f 10 hz t a = 25 c v cc = +15 v v ee = -15 v v o = 0 v r l = 10 k w t a = 25 c 0 45 90 135 180
mc34181,2,4 mc33181,2,4 http://onsemi.com 7 c l = 100 pf c l = 10 pf v cc = +15 v v ee = -15 v r l = 10 k w to -10 v < v o < +10 v figure 15. normalized gain bandwidth product versus temperature figure 16. output voltage overshoot versus load capacitance figure 17. phase margin versus load capacitance figure 18. gain margin versus load capacitance figure 19. phase margin versus temperature figure 20. gain margin versus temperature t a , ambient temperature ( c) gbw, gain bandwidth product (normalized) -55 -25 0 25 50 75 100 125 c l , load capacitance (pf) os v, output voltage overshoot (%) 10 100 1.0 k c l , load capacitance (pf) , phase margin (degrees) f m 10 100 1.0 k c l , load capacitance (pf) a m , gain margin (db) 10 100 1.0 k , phase margin (degrees) f m -55 -25 0 25 50 75 100 125 t a , ambient temperature ( c) t a , ambient temperature ( c) c l = 100 pf c l = 10 pf a m , gain margin (db) -55 -25 0 25 50 75 100 125 1.3 1.2 1.1 0.9 0.8 0.7 1.0 100 80 60 40 20 0 70 60 50 40 30 20 10 0 10 8.0 6.0 4.0 2.0 0 70 60 50 40 30 20 10 10 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 v cc = +15 v v ee = -15 v r l = 10 k w v cc = +15 v v ee = -15 v r l = 10 k w d v o = 100 mv pp -10 v < v o < +10 v a v = +1.0 t a = 25 c v cc = +15 v v ee = -15 v r l = 10 k w to -10 v < v o < +10 v t a = 25 c v cc = +15 v v ee = -15 v r l = 10 k w to -10 v < v o < +10 v t a = 25 c v cc = +15 v v ee = -15 v r l = 10 k w to -10 v < v o < +10 v
mc34181,2,4 mc33181,2,4 http://onsemi.com 8 +psr ( d v cc = 1.5 v) -psr ( d v ee = 1.5 v) +psr = 20log d v o /a dm d v cc -psr = 20log d v o /a dm d v ee v cc = +15 v v ee = -15 v t a = 25 c d v cc d v ee a dm - + d v o |i|, i , supply current (normalized) figure 21. normalized slew rate versus temperature figure 22. common mode rejection versus frequency figure 23. input noise voltage versus frequency figure 24. power supply rejection versus temperature figure 25. power supply rejection versus frequency figure 26. normalized supply current versus supply voltage t a , ambient temperature ( c) sr, slew rate (normalized) -55 -25 0 25 50 75 100 125 f, frequency (hz) cmr, common mode rejection (db) 100 1.0 k 10 k 100 k 1.0 m f, frequency (hz) e n , input noise voltage () 10 100 1.0 k 10 k 100 k nv/ hz t a < ambient temperature ( c) psr, power supply rejection (db) -55 -25 0 25 50 75 100 125 positive supply negative supply d v cc , d v ee = 3.0 v f 10 hz f, frequency (hz) psr, power supply rejection (db) 100 1.0 k 10 k 100 k 1.0 m v cc , |v ee |, supply voltage (v) ee cc 0 5.0 10 15 20 t a = 25 c 125 c -55 c 1.1 1.0 0.9 0.8 0.7 0.6 0.5 140 120 100 80 60 40 20 0 100 80 60 40 20 0 110 100 90 80 140 120 100 80 60 40 20 0 1.2 1.1 1.0 0.9 0.8 0.7 v cc = +15 v v ee = -15 v a v = +1.0 r l = 10 k w c l = 100 pf v in = -10 v to +10 v v cc = +15 v v ee = -15 v d v cm = 3.0 v t a = 25 c v cc = +15 v v ee = -15 v v cm = 0 v t a = 25 c v cc = +15 v v ee = -15 v t a = 25 c r l = v o = 0v cmr = 20 log a dm - + d v cm d v o x a dm d v cm d v o
mc34181,2,4 mc33181,2,4 http://onsemi.com 9 figure 27. channel separation versus frequency figure 28. transient response figure 29. small signal transient reponse f, frequency (hz) channel separation (db) 10 k 100 k 1.0 m 10 m v cc = +15 v v ee = -15 v t a = +25 c o v, output voltage (5.0 v/div) t, time (2.0 m s/div) o v, output voltage (20 mv/div) t, time (0.5 m s/div) v cc = +15 v v ee = -15 v r l = 10 k w a v = +1.0 t a = 25 c v cc = +15 v v ee = -15 v r l = 10 k w a v = +1.0 t a = 25 c 140 120 100 80 60 40 20 0
mc34181,2,4 mc33181,2,4 http://onsemi.com 10 p suffix plastic package case 62605 issue k d suffix plastic package case 75105 (so8) issue r outline dimensions notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. 14 5 8 f note 2 a b t seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m --- 10 --- 10 n 0.76 1.01 0.030 0.040 seating plane 1 4 5 8 a 0.25 m cb ss 0.25 m b m h c x 45 l dim min max millimeters a 1.35 1.75 a1 0.10 0.25 b 0.35 0.49 c 0.18 0.25 d 4.80 5.00 e 1.27 bsc e 3.80 4.00 h 5.80 6.20 h 0 7 l 0.40 1.25 0.25 0.50 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions are in millimeters. 3. dimension d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include mold protrusion. allowable dambar protrusion shall be 0.127 total in excess of the b dimension at maximum material condition. d e h a b e b a1 c a 0.10
mc34181,2,4 mc33181,2,4 http://onsemi.com 11 p suffix plastic package case 64606 issue l d suffix plastic package case 751a03 (so14) issue f outline dimensions continued notes: 1. leads within 0.13 (0.005) radius of true position at seating plane at maximum material condition. 2. dimension l to center of leads when formed parallel. 3. dimension b does not include mold flash. 4. rounded corners optional. 17 14 8 b a f hg d k c n l j m seating plane dim min max min max millimeters inches a 0.715 0.770 18.16 19.56 b 0.240 0.260 6.10 6.60 c 0.145 0.185 3.69 4.69 d 0.015 0.021 0.38 0.53 f 0.040 0.070 1.02 1.78 g 0.100 bsc 2.54 bsc h 0.052 0.095 1.32 2.41 j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l 0.300 bsc 7.62 bsc m 0 10 0 10 n 0.015 0.039 0.39 1.01 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b g p 7 pl 14 8 7 1 m 0.25 (0.010) b m s b m 0.25 (0.010) a s t t f r x 45 seating plane d 14 pl k c j m dim min max min max inches millimeters a 8.55 8.75 0.337 0.344 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.228 0.244 r 0.25 0.50 0.010 0.019
mc34181,2,4 mc33181,2,4 http://onsemi.com 12 on semiconductor is a trademark and is a registered trademark of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circui t, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may b e provided in scillc data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its paten t rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc34181/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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